This invention relates to an analog-to-digital converting method and, more particularly, to an analog-to-digital converting (ADC) method that is mainly used in pulse-height analyzers.
This invention aims, in a converting system wherein an analog signal is once converted into a time signal and, thereafter, the time signal is converted into a digital value, to achieve improvement in the conversion characteristics and increase the conversion ability. Furthermore, the construction of a time-to-digital conversion of this invention can, as itself, be applied to increase the conversion ability of a time analyzer used as a time-to-digital converting (TDC) circuit.
In the TDC circuit, such as a pulse-height analyzer, used as an instrument wherein a number of input signals are continuously measured and wherein the result of measurements is summed to make a histogram to obtain a measurement resultant, it is an absolutely inevitable condition to establish good integral non-linearity as well as good differential non-linearity that denotes the uniformity that the width of each channel ("channel" is, hereinafter referred to as a digitalized value) occupies on the abscissa of the histogram.
A counting process, which is generally referred to as Wilkinson process in the nuclear field, for gating clock-pulses by the time signals is generally used in order to obtain good differential non-linearity. However, the differential non-linearity is deteriorated due to some causes as the frequency of the clock-pulses is expedited due to a request for quickening the conversion time, and, therefore, the process cannot be practically used when the differential non-linearity exceeds an allowable limit.
In an ADC circuit of the prior art, as shown in FIG. 1, wherein analog signals are converted into time signals and clock-pulses are gated by the time signals, the clock-pulses are obtained accurately and this method can basically provide good differential non-linearity. Therefore, no countermeasure is normally considered to maintain the good differential non-linearity.
This causes the differential non-linearity to be deteriorated due to some interfering action as the frequency of the clock-pulses is expedited. The interfering action is brought about in the TDC in FIG. 1 and the period of the clock-pulses is disturbed due to the interfering action of the operation in every order of a scaler at every clock-pulse. This is discussed in more detail in the following:
For example, in the circuit shown in FIG. 2, where the TDC is effected by a binary scaler, time signals are applied to a gate 4 from a terminal 1 and clock-pulses obtained from a clock oscillator 2 are also applied to gate 4 from a terminal 3. The clock-pulses are gated at gate 4 to provide outputs at a terminal 5 and the outputs are applied to a scaler 6 to be counted. Digital values are obtained at a terminal 7 as the outputs of scaler 6 which are proportional to the time signals.
During these operations, a first stage binary 8 of scaler 6 induces at a terminal 9 an output of period of twice the clock-pulses applied at terminal 5. An output of period of four times the clock-pulses is induced at a terminal 11 by a second stage binary 10 of scaler 6 so that a so-called binary counting operation is effected.
First stage binary 8 has a period of twice the clock-pulses, as stated above, and the pulses of twice period trigger second stage binary 10 and, at the same time, provide an action of interference to clock oscillator 2, terminal 3, terminal 5 and gate 4 from first stage binary 8. An action of interference, similar to the above, is provided in the binary which is in and after second stage binary 10 so that an action of interference of a period of four times and eight times, etc., the clock-pulses are provided on terminal 3.
Thus, the period of the clock-pulses are naturally disturbed by receiving an induction of low frequency component and, for example, when a low frequency component of twice period is induced by the first stage binary, a wide period and a narrow period will alternately be generated every other cycle. If the clock-pulses are gated by such unbalanced period the probability that the scaler stops after termination of counting will naturally be higher in the range that the wide period appears. Thus an unbalance in ratio where an even number and an odd number appear naturally exists in the digital value thus obtained. A phenomenon similar to the above will be brought about in and after the second stage binary of the scaler so that the resultant action of interference deteriorates the differential linearity.
The degree of the action of interference varies in accordance with the sort of elements used, amplitudes of element signals, propagation time in the elements, arrangement of circuits or construction of circuits and the higher the rate of the clock-pulses the larger the degree of the action of interference so the differential linearity is accordingly deteriorated.
The known countermeasure taken in order to solve these problems is that the gate is made to open and close in synchronization with the clock-pulses to assure the operation of the gate or that the scaler is triggered by an output coming from a binary which is added after the gate circuit. In the former, the gate operation can be synchronized with the clock-pulses but the ending time of the time signal occurs at an arbitrary relation to the phase of the clock-pulses so that it is difficult to provide a complete operation and, moreover, when the period of the clock-pulses applied to the gate is disturbed the unbalance in the digital values remains unsolved. In the latter, the odd-even unbalance which is the most affective is avoided to some degree but the action of interference coming from the first stage binary or the second stage binary or any further stage binaries in the scaler is not only solved but it becomes necessary to operate the clock oscillator and the gates at a speed of twice that of the scaler. Moreover, it is necessary to use high speed elements when the scaler is operating at a high speed so that a number of bad influences remain unsolved.
Furthermore, the frequencies of the clock-pulses are generally limited to below the highest operating speed of one or more of the high speed elements.
The present status is, as stated above, that it is compromised to lower the rate of the clock-pulses within a range that the differential non-linearity is allowable to effect a time-to-digital conversion, since there is a limit in raising the rate of the clock-pulses in view of the differential non-linearity.
No remarkable countermeasure such as that stated above has yet been utilized in the ADC of the counting type. However, in the field of the ADC of the sliding scale type Mr. E. Gatti et al has effectively improved the differential non-linearity as shown in U.S. Pat. No. 3,386,090.
The method improved by Gatti is not applied to any or prior ADC of the counting type without modification. If the Gatti method is forced to be applied thereto, no useful result is obtained. The reason is based on the fact that in the sliding scale type ADC the deviation in the accuracy of the elements that determine the analog quantity affects the differential non-linearity in the digital-to-analog converting (DAC) circuit which constitutes the ADC and the deviation exists constant and continuously in time as the deviation in the analog quantity. The countermeasure as shown in U.S. Pat. No. 3,386,090 is considered to be proper on the premise that a condition stated above exists.
On the contrary, in the counting type ADC of prior art, an interfering operation or action is left as a deviation at the moment when the conversion and counting terminates and, therefore, the mechanism of deviation generation is different with each other between the prior art counting type ADC and this invention.
Accordingly, even if an adding operation and a subtracting operation are effected by dividing the values shown in U.S. Pat. No. 3,386,090 into the analog value and the digital value, no averaging operation can be brought about nor the differential non-linearity can be improved.